Monolithic Darlington with Intermediate Base Contact

ABSTRACT

In one embodiment, a method includes forming a first pad for coupling to a first terminal of a first transistor of a monolithic darlington transistor configuration and forming a second pad for coupling to a first terminal of a second transistor of the monolithic darlington transistor configuration. The method then forms a third pad for coupling to an external component for the monolithic darlington transistor configuration. The third pad is coupled to a second terminal of the first transistor and a second terminal of the second transistor of the monolithic darlington transistor configuration.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional App. No. 61/424,956 for “Darlington with Intermediate Base Contact” filed Dec. 20, 2010, the contents of which is incorporated herein by reference in their entirety.

BACKGROUND

Particular embodiments generally relate to Monolithic Darlington transistor configurations.

There is no provision to make an external connection to the intermediate base/emitter regions of monolithic darlingtons. The intermediate node is in between an input and an output for a package. The intermediate node is inside the package and it is not possible to connect external components to the intermediate base/emitter regions of monolithic darlingtons. Such a connection would sacrifice valuable silicon real estate.

SUMMARY

In one embodiment, a method includes forming a first pad for coupling to a first terminal of a first transistor of a monolithic darlington transistor configuration and forming a second pad for coupling to a first terminal of a second transistor of the monolithic darlington transistor configuration. The method then forms a third pad for coupling to an external component for the monolithic darlington transistor configuration. The third pad is coupled to a second terminal of the first transistor and a second terminal of the second transistor of the monolithic darlington transistor configuration.

In one embodiment, a method includes: forming a first pad for coupling an input node of a first die to a first transistor of a first die; forming a second pad for coupling an output node of the first die to a second transistor; and forming a third pad configured to be coupled to a third transistor of a second die, wherein the third pad couples to an intermediate node between the input node and the output node.

In one embodiment, an apparatus includes: a first pad for coupling to a first terminal of a first transistor of a monolithic darlington transistor configuration; a second pad for coupling to a first terminal of a second transistor of the monolithic darlington transistor configuration; and a third pad for coupling to an external component for the monolithic darlington transistor configuration, the third pad being coupled to a second terminal of the first transistor and a second terminal of the second transistor of the monolithic darlington transistor configuration.

The following detailed description and accompanying drawings provide a better understanding of the nature and advantages of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts a simplified view of a chip according to one embodiment.

FIG. 2 depicts a circuit of a Darlington transistor configuration according to one embodiment.

DETAILED DESCRIPTION

Described herein are techniques for a monolithic Darlington transistor configuration. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

FIG. 1 depicts a simplified view of a chip 200 for a circuit according to one embodiment. As shown, an additional pad 202 is formed. A pad 204 is coupled to an input of the circuit. A pad 206 is coupled to the output of the circuit.

Pad 202 is coupled to the both the intermediate emitter of a first transistor and the intermediate base of a second transistor. This pad 202 allows a connection of any external component to the linked intermediate emitter and base. The external connection may be a wire that couples the base of second transistor to the base of a fourth transistor. Conventionally, the base of second transistor was inaccessible because it is an intermediate connection. That is, it is a connection internal to the package, not like the input or the output. The base of the fourth transistor may also be an intermediate connection with an emitter of a third transistor. In one embodiment, the layout may be altered to allow room for pad 202 to be included. For example, layers in a design are truncated in the region of pad 202. If pad 202, the function provided by the features that are truncated (underneath pad 202) cannot assist in the function that they would have performed, and the function is provided elsewhere in the chip. For example, the chip is enlarged elsewhere to compensate.

Chip 200 may be part of a monolithic configuration, which means that the first transistor and the second transistor may be included in a single die and third transistor and the fourth transistor may be included in a single die. Thus, the extra pad 202 may be found on both dies. A wire connection the extra pad 202 of both dies may then be used to couple the bases of the second transistor and the fourth transistor together.

Additional pads may also be included. The darlingtons may be cascaded in which case additional pads may or may not be provided such that each intermediate base may or may not be connected to an additional component in which may be any one of other intermediate bases of either transistor of the complimentary device in the darlington pair.

FIG. 2 depicts a circuit 100 of a Darlington transistor configuration according to one embodiment. Circuit 100 may use extra pad 202 to couple the bases of transistor Q11 OUT and Q12 OUT. However, other circuit configurations may be used to couple intermediate nodes of transistors. In one embodiment, the Darlington transistor configuration is a complementary Darlington emitter follower pair. Circuit 100 may be used to drive MOSFET and Insulated gate bipolar transistor (IGBT) gates with a high current gain. As shown, circuit 100 includes a first transistor Q11 IN and a second transistor Q11 OUT that may be considered a first Darlington. A complementary Darlington or emitter follower may include transistor Q11 IN and transistor Q12 OUT. In one embodiment, circuit 100 may be a monolithic Darlington configuration. The monolithic configuration means that transistor Q11 IN and Q11 OUT may be included in a single die and transistor Q12 IN and transistor Q12 OUT may be included in a single die. Both dies may be included in a single device. Also, it will be understood that even though a Darlington configuration is described, other similar configurations may be used, such as a triplington or other multiple transistor configurations in a Darlington configuration. Also, NPN and PNP variations of the Darlington transistor configuration may vary.

In circuit 100, an input is coupled to the base of transistor Q11 IN and the base of transistor Q12 IN. Also, an output is coupled to the emitters of transistor Q11 OUT and transistor Q12 OUT. The emitters of transistors Q11 OUT and Q12 OUT may be connected together (shorted) or left unconnected in which case there are two output nodes. Particular embodiments add a link between the base of transistor Q11 OUT and the base of transistor Q12 OUT. The added link may be a wire that provides a short. Adding the link eliminates or reduces a very large wasted shoot-through current at a crossover. At a point in the switching cycle where transistor's Q11 OUT state is being changed from conducting to non-conducting and transistor Q12 OUT is changing from non conducting to conducting, transistor Q11 OUT should turn off at exactly the same time that transistor Q12 OUT turns on. However, due to charge stored in the base of transistor Q11 OUT, transistor Q11 OUT remains turned “ON” for a finite time during which time transistor Q12 OUT and transistor Q11 OUT are both ON simultaneously and present a very low resistance path to ground. During this time, very large shoot through currents flow from supply to ground. These currents are wasted energy and reduce the efficiency of the circuit. The provision of the short from the base of transistor Q11 OUT to the emitter of transistor Q12 IN provides a very effective route for removal of the stored charge and thus eliminates the possibility of transistor Q11 OUT remaining turned on for long enough to permit the flow of the shoot through currents. An identical situation exists when transistor Q12 OUT is turning off and transistor Q11 OUT is turning on.

Also, circuit 100 provides a highest possible switching speed and the highest possible rail to rail excursion. The highest switch speed is due to being able to discharge transistor Q11 OUT or transistor Q12 OUT quickly with the added link. In addition, a turn-off voltage is lowered to about 0.5V and also the turn-on voltage is within 0.5V of supply Vcc. Conventionally, the turn off voltage or turn on voltage would not be lower than one VBE+one VCESAT˜0.9V, where VBE is the base-emitter voltage and VCESAT is the collector-emitter voltage at saturation. This is because the base of the output transistor Q11 OUT or transistor Q12 OUT is required to be at approximately 0.7V above its emitter voltage for base current to flow to create current flow in its emitter-collector circuit. Additionally this base current is supplied by the input transistor Q12 IN via its emitter-collector circuit. In a monolithic darlington configuration the collector of the input transistor Q12 IN is connected to the collector of the output transistor Q12 OUT. Hence the voltage difference between the emitter of transistor Q12 IN (which is also the base of transistor Q12 OUT) and its collector cannot be less than the VCESAT of transistor Q12 IN, say 0.2V, otherwise transistor Q12 IN will not conduct the needed base current into the base of transistor Q12 OUT. Given that the emitter of transistor Q12 OUT has to be approximately 0.7V below its base and its base has to be 0.2V below its collector then the collector emitter voltage of transistor Q12 OUT when conducting cannot be less than approximately 0.7V plus 0.2V, that is—VBESAT(of transistor Q12 OUT) plus VCESAT(of transistor Q12 IN).

As discussed above, a wire may be used to couple the base of transistor Q11 OUT and the base of transistor Q12 OUT together. The wire permits the characteristics of the Darlingtons to be modified as desired. Additional components other than the wire may be added with the wire or used in lieu of the wire.

As will be described in more detail below, additional pad may be provided such that the wire may be added to link transistor Q11 OUT and transistor Q12 OUT. The Darlingtons may be cascaded where additional pads may or may not be provided such that each intermediate base may or may not be connected to an additional component.

Without using the added link, it is possible that transistors Q11 OUT and Q12 OUT were on at the same time. This is because the bases of transistor Q11 OUT and transistor Q12 OUT do not have a low resistance route by which charge stored in their bases can be removed rapidly. Whichever transistor is turned “ON” contains significant stored charge that must be removed before its voltages will start to change. If the base bias difference reaches around 1.2V, both transistors Q11 OUT and Q12 OUT are on. This causes a current to flow from power supply Vcc to ground through transistors Q11 OUT and Q12 OUT. This is a high parasitic current, which wastes power.

The link causes the bases of transistors Q11 OUT and Q12 OUT to be at the same voltage and provides a route for the rapid removal of the stored base charge. Thus, transistor Q11 OUT and transistor Q12 OUT do not turn on at the same time. Thus, a very large parasitic current does not flow from power supply Vcc to ground.

The added link also allows the switching performance of the Darlington transistor to be fast. The switching performance may be dependent upon charge stored in the base region of transistor Q11 OUT. If the base region of transistor Q11 OUT is floating, then the time in which the charge can dissipate may limit switching times to turn off transistor Q11 OUT from an on state. However, the added link allows charge to be dissipated faster from the base region to turn off transistor Q11 OUT. For example, transistor Q12 IN turns on, and couples the base of transistor Q11 OUT to ground. This dissipates the charge at the base of transistor Q11 OUT to decrease the switching time to turn off transistor Q11 OUT. The discharge is performed for transistor Q12 OUT through transistor Q11 IN but in the opposite direction.

As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims. 

1. A method comprising: forming a first pad for coupling to a first terminal of a first transistor of a monolithic darlington transistor configuration; forming a second pad for coupling to a first terminal of a second transistor of the monolithic darlington transistor configuration; and forming a third pad for coupling to an external component for the monolithic darlington transistor configuration, the third pad being coupled to a second terminal of the first transistor and a second terminal of the second transistor of the monolithic darlington transistor configuration.
 2. The method of claim 1, wherein: the first terminal of the first transistor is a base terminal; the second terminal of the first transistor is an emitter terminal; the first terminal of the second transistor is an emitter terminal; the second terminal of the second transistor is a base terminal.
 3. The method of claim 1, wherein: the first terminal of the first transistor is coupled to an input of a die including the monolithic darlington transistor configuration; and the first terminal of the second transistor is coupled to an output of the die including the monolithic darlington transistor configuration.
 4. The method of claim 3, wherein the second terminal of the first transistor is coupled to the second terminal of the second transistor at an intermediate node between the input and the output of the die.
 5. The method of claim 1, wherein: forming a fourth pad for coupling to a first terminal of a third transistor of the monolithic darlington transistor configuration; forming a fifth pad for coupling to a first terminal of a fourth transistor of the monolithic darlington transistor configuration; and forming a sixth pad for coupling to an external component for the monolithic darlington transistor configuration, the sixth pad being coupled to a second terminal of the third transistor and a second terminal of the fourth transistor of the monolithic darlington transistor configuration.
 6. The method of claim 5, further comprising coupling the third pad to the sixth pad with a wire.
 7. The method of claim 5, further comprising coupling the second terminal of the first transistor and the second terminal of the second transistor to the second terminal of the third transistor and the second terminal of the fourth transistor through the third pad and the sixth pad.
 8. A method comprising: forming a first pad for coupling an input node of a first die to a first transistor of a first die; forming a second pad for coupling an output node of the first die to a second transistor; and forming a third pad configured to be coupled to a third transistor of a second die, wherein the third pad couples to an intermediate node between the input node and the output node.
 9. The method of claim 8, wherein: the input node is coupled to a base of the first transistor, the output node is coupled to an emitter of the second transitor, and the intermediate node is coupled to an emitter of the first transistor and a based on the second transistor.
 10. The method of claim 8, further comprising: forming a fourth pad for coupling an input node of the second die to a fourth transistor; forming a fifth pad for coupling an output node of the second die to the third transistor; and forming a sixth pad configured to be coupled to the second transistor of the first die, wherein the sixth pad couples to an intermediate node between the input node and the output node of the second die.
 11. An apparatus comprising: a first pad for coupling to a first terminal of a first transistor of a monolithic darlington transistor configuration; a second pad for coupling to a first terminal of a second transistor of the monolithic darlington transistor configuration; and a third pad for coupling to an external component for the monolithic darlington transistor configuration, the third pad being coupled to a second terminal of the first transistor and a second terminal of the second transistor of the monolithic darlington transistor configuration.
 12. The apparatus of claim 11, wherein: the first terminal of the first transistor is a base terminal; the second terminal of the first transistor is an emitter terminal; the first terminal of the second transistor is an emitter terminal; the second terminal of the second transistor is a base terminal.
 13. The apparatus of claim 11, wherein: the first terminal of the first transistor is coupled to an input; and the first terminal of the second transistor is coupled to an output.
 14. The apparatus of claim 11, wherein: the second terminal of the first transistor is coupled to the second terminal of the second transistor at an intermediate node of the monolithic darlington transistor configuration.
 15. The apparatus of claim 11, further comprising: a fourth pad for coupling to a first terminal of a third transistor of the monolithic darlington transistor configuration; a fifth pad for coupling to a first terminal of a fourth transistor of the monolithic darlington transistor configuration; and a sixth pad for coupling to an external component for the monolithic darlington transistor configuration, the sixth pad being coupled to a second terminal of the third transistor and a second terminal of the fourth transistor of the monolithic darlington transistor configuration.
 16. The apparatus of claim 15, wherein the third pad is coupled to the sixth pad with a wire.
 17. The apparatus of claim 15, wherein the second terminal of the first transistor and the second terminal of the second transistor is coupled to the second terminal of the third transistor and the second terminal of the fourth transistor through the third pad and the sixth pad. 